A successive-approximation converter is a feedback system which operates on a trial-and-error technique to approximate an analog input with a corresponding digital code. The system is comprised of a so-called successive approximation register (SAR) and a D/A converter in feedback around a voltage comparator.
In general, with reference to FIG. 1, an SA-ADC converter operates as follows. Prior to the start of the conversion process, an N-bit sequencer or shift register and an N-bit holding register which form the successive-approximation register section are cleared. In the first step of conversion, a "1" is inserted as a trial bit for the MSB in the holding register, with the rest of the bits remaining at "0". If the resulting analog output of the D/A converter Vref is less than or equal to the Vin, the output state of the comparator remains unchanged and the "1" is retained for the MSB; otherwise it is replaced by a "0".
Then, in the next cycle, a "1" is tried for the second significant bit. If the comparator output does not change state, it is retained; otherwise it is replaced by a "0". In this manner, the approximation process is repeated until all bits are calculated in N successive cycles. A general description of the prior art appears in A. Grebene, Bipolar and MOS Analog Integrated Circuit Design (John Wiley & Sons, Inc., 1984), chapter 15.
In a sampled ADC circuit, a sample step is conducted prior to beginning the actual conversion. During sampling, an input voltage or "sample voltage" is stored on a sample capacitor. The capacitor is coupled to one side of a differential pair of transistors forming the comparator input stage. A bias current source provides a predetermined bias current Io to the comparator input stage differential pair of transistors (M1, M2). A typical comparator input stage schematic is shown in FIG. 2.
Referring now to FIG. 2, the driven input voltage, or reference voltage Vref, is applied to the gate of M2 (REF). Vref is provided by a DAC converter (not shown) disposed in a feedback loop from the comparator (see FIG. 1). The reference voltage typically has a fast rise time. As a result, parasitic gate capacitances of M1 and M2, labeled Cgs1 and Cgs2, respectively, couple the changing Vref through M2 to the common drain node V1, and thence through M1 back to the sample input node Vin. This charge injection current results in a change in the charge on C, and hence a change in the sample voltage Vin. Thus, EQU .DELTA.Vref.fwdarw..DELTA.Q where Q is the charge on C, and[1] EQU .DELTA.Q.fwdarw..DELTA.Vin=.DELTA.Q/C [2]
The resulting change in Vin, an input offset source of error, is a function of the difference between Vref and Vin when the sample is taken. The error can be large, because the reference voltage can swing over the entire common mode range, for example, 10 volts.
To illustrate, assume Vin=+10 and Vref=0 at sample time. At this time, the common source node is roughly a threshold voltage above Vref. At the end of conversion Vref=Vin' where Vin'=Vin+.DELTA.V1 Cgs1/C, the error term being due to the change in V1 with respect to Vin.
If we approximate .DELTA.V1.apprxeq.Vin-10 V, the error term Vin-Vin'.apprxeq.(Vin-10 V). Cgs1/C. Typical values of Cgs1 and C are 100 ffd and 10 pfd respectively, generating offset voltages up to around 100 mV for a 10 analog input range. It is difficult to compensate for the injected current offset because it depends upon the sample voltage Vin. What is needed is a sampled ADC that does not suffer inaccuracies resulting from charge injection.